APPENDIX A: ALTAIR 8800 INSTRUCTION SET

Definitions:

DDD	Destination Register
SSS	Source Register
rp	Register Pair

Register Designations

Register (SSS or DDD)	Bit Pattern
B	000
C	001
D	010
E	011
H	100
L	101
Memory	110
Accumulator	111

Register Designations

Register Pair	Bit Pattern
B and C	00
D and E	01
H and L	10
SP	11

A. COMMAND INSTRUCTIONS

1. Input/Output Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
IN	2	3	11 011 011	333	DB
OUT	2	3	11 010 011	323	D3

2. Interrupt Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
EI	1	1	11 111 011	373	FB
DI	1	1	11 110 011	363	F3
HLT	1	1	01 110 110	166	76
RST	1	3	11 (exp) 111	3(exp)7
RST 0			11 000 111	3 0 7	C7
RST 1			11 001 111	3 1 7	CF
RST 2			11 010 111	3 2 7	D7
RST 3			11 011 111	3 3 7	DF
RST 4			11 100 111	3 4 7	E7
RST 5			11 101 111	3 5 7	EF
RST 6			11 110 111	3 6 7	F7
RST 7			11 111 111	3 7 7	FF

3. Carry Bit Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
CMC	1	1	00 111 111	077	3F
STC	1	1	00 110 111	067	37

4. No Operation Instruction

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
NOP	1	1	00 000 000	000	00

B. SINGLE REGISTER INSTRUCTIONS

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
INR	1	3	00 (DDD) 100	0(DDD)4
INR B			00 000 100	0 0 4	04
INR C			00 001 100	0 1 4	0C
INR D			00 010 100	0 2 4	14
INR E			00 011 100	0 3 4	1C
INR H			00 100 100	0 4 4	24
INR L			00 101 100	0 5 4	2C
INR M			00 110 100	0 6 4	34
INR A			00 111 100	0 7 4	3C
DCR	1	3	00 (DDD) 101	0(DDD)5
DCR B			00 000 101	0 0 5	05
DCR C			00 001 101	0 1 5	0D
DCR D			00 010 101	0 2 5	15
DCR E			00 011 101	0 3 5	1D
DCR H			00 100 101	0 4 5	25
DCR L			00 101 101	0 5 5	2D
DCR M			00 110 101	0 6 5	35
DCR A			00 111 101	0 7 5	3D
CMA	1	1	00 101 111	057	2F
DAA	1	1	00 100 111	047	27

C. REGISTER PAIR INSTRUCTIONS

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
PUSH	1	3	11 (rp)0 101	3(rp)5
PUSH B			11 000 101	3 0 5	C5
PUSH D			11 010 101	3 2 5	D5
PUSH H			11 100 101	3 4 5	E5
PUSH PSW			11 110 101	3 6 5	F5
POP	1	3	11 (rp)0 001	3(rp)1
POP B			11 000 001	3 0 1	C1
POP D			11 010 001	3 2 1	D1
POP H			11 100 001	3 4 1	E1
POP PSW			11 110 001	3 6 1	F1
DAD	1	3	00 (rp)1 001	0(rp)1
DAD B			00 001 001	3 1 1	09
DAD D			00 011 001	3 3 1	19
DAD H			00 101 001	3 5 1	29
DAD SP			00 111 001	3 7 1	39
INX	1	1	00 (rp)0 011	0(rp)3
INX B			00 000 011	0 0 3	03
INX D			00 010 011	0 2 3	13
INX H			00 100 011	0 4 3	23
INX SP			00 110 011	0 6 3	33
DCX	1	1	00 (rp)1 011	0(rp)3
DCX B			00 001 011	0 1 3	0B
DCX D			00 011 011	0 3 3	1B
DCX H			00 101 011	0 5 3	2B
DCX SP			00 111 011	0 7 3	3B
XCHG	1	1	11 101 011	353	EB
XTHL	1	5	11 100 011	343	E3
SPHL	1	1	11 111 001	371	F9

D. ROTATE ACCUMULATOR INSTRUCTIONS

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
RLC	1	1	00 000 111	007	07
RRC	1	1	00 001 111	017	0F
RAL	1	1	00 010 111	027	17
RAR	1	1	00 011 111	037	1F

E. DATA TRANSFER INSTRUCTIONS

1. Data Transfer Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
MOV	1	1 or 2	01 (DDD) (SSS)	1(DDD)(SSS)
MOV B,B			01 000 000	1 0 0	40
MOV B,C			01 000 001	1 0 1	41
MOV B,D			01 000 010	1 0 2	42
MOV B,E			01 000 011	1 0 3	43
MOV B,H			01 000 100	1 0 4	44
MOV B,L			01 000 101	1 0 5	45
MOV B,M			01 000 110	1 0 6	46
MOV B,A			01 000 111	1 0 7	47
MOV C,B			01 001 000	1 1 0	48
There are 46 additional variants of the MOV instruction. (Total: 64)
MOV M,A			01 110 111	1 6 7	77
MOV A,B			01 111 000	1 7 0	78
MOV A,C			01 111 001	1 7 1	79
MOV A,D			01 111 010	1 7 2	7A
MOV A,E			01 111 011	1 7 3	7B
MOV A,H			01 111 100	1 7 4	7C
MOV A,L			01 111 101	1 7 5	7D
MOV A,M			01 111 110	1 7 6	7E
MOV A,A			01 111 111	1 7 7	7F
STAX	1	2	00 0(X)0 010	0(X)2
STAX B			00 000 010	0 0 2	02
STAX D			00 010 010	0 2 2	12
LDAX	1	2	00 0(X)1 010	0(X)2
LDAX B			00 001 010	0 1 2	0A
LDAX D			00 011 010	0 3 2	1A

Note

Register Pair B and C–0 at X

Register Pair D and E–1 at X

2. Register/Memory to Accumulator Transfers

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
ADD	1	1	10 000 (SSS)	20(SSS)
ADD B			10 000 000	2 0 0	80
ADD C			10 000 001	2 0 1	81
ADD D			10 000 010	2 0 2	82
ADD E			10 000 011	2 0 3	83
ADD H			10 000 100	2 0 4	84
ADD L			10 000 101	2 0 5	85
ADD M			10 000 110	2 0 6	86
ADD A			10 000 111	2 0 7	87
ADC	1	1	10 001 (SSS)	21(SSS)
ADC B			10 001 000	2 1 0	88
ADC C			10 001 001	2 1 1	89
ADC D			10 001 010	2 1 2	8A
ADC E			10 001 011	2 1 3	8B
ADC H			10 001 100	2 1 4	8C
ADC L			10 001 101	2 1 5	8D
ADC M			10 001 110	2 1 6	8E
ADC A			10 001 111	2 1 7	8F
SUB	1	1	10 010 (SSS)	22(SSS)
SUB B			10 010 000	2 2 0	90
SUB C			10 010 000	2 2 1	91
SUB D			10 010 000	2 2 2	92
SUB E			10 010 000	2 2 3	93
SUB H			10 010 000	2 2 4	94
SUB L			10 010 000	2 2 5	95
SUB M			10 010 000	2 2 6	96
SUB A			10 010 000	2 2 7	97
SBB	1	1	10 011 (SSS)	23(SSS)
SBB B			10 011 000	2 3 0	98
SBB C			10 011 000	2 3 1	99
SBB D			10 011 000	2 3 2	9A
SBB E			10 011 000	2 3 3	9B
SBB H			10 011 000	2 3 4	9C
SBB L			10 011 000	2 3 5	9D
SBB M			10 011 000	2 3 6	9E
SBB A			10 011 000	2 3 7	9F
ANA	1	1	10 100 (SSS)	24(SSS)
ANA B			10 100 000	2 4 0	A0
ANA C			10 100 000	2 4 1	A1
ANA D			10 100 000	2 4 2	A2
ANA E			10 100 000	2 4 3	A3
ANA H			10 100 000	2 4 4	A4
ANA L			10 100 000	2 4 5	A5
ANA M			10 100 000	2 4 6	A6
ANA A			10 100 000	2 4 7	A7
XRA	1	1	10 101 (SSS)	25(SSS)
XRA B			10 101 000	2 5 0	A8
XRA C			10 101 000	2 5 1	A9
XRA D			10 101 000	2 5 2	AA
XRA E			10 101 000	2 5 3	AB
XRA H			10 101 000	2 5 4	AC
XRA L			10 101 000	2 5 5	AD
XRA M			10 101 000	2 5 6	AE
XRA A			10 101 000	2 5 7	AF
ORA	1	1	10 110 (SSS)	26(SSS)
ORA B			10 110 000	2 6 0	B0
ORA C			10 110 000	2 6 1	B1
ORA D			10 110 000	2 6 2	B2
ORA E			10 110 000	2 6 3	B3
ORA H			10 110 000	2 6 4	B4
ORA L			10 110 000	2 6 5	B5
ORA M			10 110 000	2 6 6	B6
ORA A			10 110 000	2 6 7	B7
CMP	1	1	10 111 (SSS)	27(SSS)
CMP B			10 111 000	2 7 0	B8
CMP C			10 111 000	2 7 1	B9
CMP D			10 111 000	2 7 2	BA
CMP E			10 111 000	2 7 3	BB
CMP H			10 111 000	2 7 4	BC
CMP L			10 111 000	2 7 5	BD
CMP M			10 111 000	2 7 6	BE
CMP A			10 111 000	2 7 7	BF

3. Direct Addressing Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
STA	3	4	00 110 010	062	32
LDA	3	4	00 111 010	072	3A
SHLD	3	5	00 100 010	042	22
LHLD	3	5	00 101 010	052	2A

F. IMMEDIATE INSTRUCTIONS

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
LXI	3	3	00 (rp)0 001	0(rp)1
LXI B			00 000 001	0 0 1	01
LXI D			00 010 001	0 1 1	11
LXI H			00 100 001	0 2 1	21
LXI SP			00 110 001	0 3 1	31
MVI	2	2 or 3	00 (SSS) 110	0(SSS)6
MVI B			00 000 110	0 0 6	06
MVI C			00 001 110	0 1 6	0E
MVI D			00 010 110	0 2 6	16
MVI E			00 011 110	0 3 6	1E
MVI H			00 100 110	0 4 6	26
MVI L			00 101 110	0 5 6	2E
MVI M			00 110 110	0 6 6	36
MVI A			00 111 110	0 7 6	3E
ADI	2	2	11 000 110	306	C6
ACI	2	2	11 001 110	316	CE
SUI	2	2	11 010 110	326	D6
SBI	2	2	11 011 110	336	DE
ANI	2	2	11 100 110	346	E6
XRI	2	2	11 101 110	356	EE
ORI	2	2	11 110 110	366	F6
CPI	2	3	11 111 110	376	FE

G. BRANCHING INSTRUCTIONS

1. Jump Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
PCHL	1	1	11 101 001	351	E9
JMP	3	3	11 000 011	303	C3
JC	3	3	11 011 010	332	DA
JNC	3	3	11 010 010	322	D2
JZ	3	3	11 001 010	312	CA
JNZ	3	3	11 000 010	302	C2
JM	3	3	11 111 010	372	FA
JP	3	3	11 110 010	362	F2
JPE	3	3	11 101 010	352	EA
JPO	3	3	11 100 010	342	E2

2. Call Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
CALL	3	5	11 001 101	315	CD
CC	3	3 or 5	11 011 100	334	DC
CNC	3	3 or 5	11 010 100	324	D4
CZ	3	3 or 5	11 001 100	314	CC
CNZ	3	3 or 5	11 000 100	304	C4
CM	3	3 or 5	11 111 100	374	FC
CP	3	3 or 5	11 110 100	364	F4
CPE	3	3 or 5	11 101 100	354	EC
CPO	3	3 or 5	11 100 100	344	E4

3. Return Instructions

Mnemonic	Bytes	Cycles	Binary Code	Octal Code	Hex Code
RET	1	3	11 001 001	311	C9
RC	1	1 or 3	11 011 000	330	D8
RNC	1	1 or 3	11 010 000	320	D0
RZ	1	1 or 3	11 001 000	310	C8
RNZ	1	1 or 3	11 000 000	300	C0
RM	1	1 or 3	11 111 000	370	F8
RP	1	1 or 3	11 110 000	360	F0
RPE	1	1 or 3	11 101 000	350	E8
RPO	1	1 or 3	11 100 000	340	E0