PART 4. ALTAIR 8800 INSTRUCTION SET
The ALTAIR 8800 has 78 basic machine language instructions. Since
many of the instructions can be modified to affect different registers
or register pairs, more than 200 variances of the basic instructions
are possible.
A detailed description of the ALTAIR 8800 instruction set is
provided in the remainder of this operating manual. For the purpose
of this description, the 78 basic machine language instructions have
been grouped into seven major subdivisions:
- Command Instructions
- Single Register Instructions
- Register Pair Instructions
- Rotate Accumulator Instructions
- Data Transfer Instructions
- Immediate Instructions
- Branching Instructions
Each instruction is presented as a standardized mnemonic or machine
language code. Instructions may occupy from one to three sequential
(serial) bytes, and the appropriate bit patterns are included. A
condensed summary of the complete instruction set showing the
mnemonics and instructions in both binary and octal is included as
an Appendix.
A. COMMAND INSTRUCTIONS
The ALTAIR 8800 has nine special purpose command instructions which
are used to service the remaining instructions. These special purpose
instructions occupy four catagories: Input/Output Instructions
(IN, OUT), Interrupt Instructions (EI, DI, HLT,
RST), Carry Bit Instructions (STC, CMC), and the No
Operation Instruction (NOP).
2. INTERRUPT INSTRUCTIONS
There are two specific Interrupt instructions (EI and DI) and
two auxiliary Interrupt instructions. Interrupt instructions permit
implementation of a program by a computer to be temporarily
interrupted so that input/output interfacing may take place. For
example, interrupts may be utilized by a computer’s output device
while an input device is entering data or a program.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
EI |
ENABLE INTERRUPTS |
11 111 011 |
(Byte 1) |
Operation: Implementation of the EI instruction sets the
interrupt flip-flop. This alerts the computer to the presence of
interrupts and causes it to respond accordingly. |
| Status Bits: Unaffected. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
DI |
DISABLE INTERRUPTS |
11 110 011 |
(Byte 1) |
Operation: Implementation of the DI instruction resets
the interrupt flip-flop. This causes the computer to ignore any
subsequent interrupt signals. |
| Status Bits: Unaffected. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
HLT |
HALT INSTRUCTION |
01 110 110 |
(Byte 1) |
Operation: Implementation of the HLT instruction steps
the Program Counter to the next instruction address and stops the
computer until an interrupt occurs. The HLT instruction
should not normally be implemented when a DI instruction has
been executed. Since the DI instruction causes the computer
to ignore interrupts, the computer will not operate again until
the main power switch is turned off and then back on. |
| Status Bits: Unaffected. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RST |
RESTART INSTRUCTION |
11 (exp)
111 |
(Byte 1) |
Operation: The data byte in the Program Counter is pushed
onto the stack. This provides an address for subsequent use by
a RETURN instruction. Program execution then continues at
memory address: 00 000 000 00 (exp) 000 where exp ranges
from 000 to 111.
The RST instruction is normally used to service interrupts.
The external device may cause a RST instruction to be executed
during an interrupt. Implementation of RST then calls a special
purpose subroutine which is stored in up to eight 8-bit bytes in the
lower 64 words of memory. A RETURN instruction is included to
return the computer to the original program.
|
| Status Bits: Unaffected. |
Example: Assume the following RST instruction is present:
11 001 111. Implementation of the instruction will cause the
Program Counter data byte to be pushed onto the stack. The program
will then continue execution at the subroutine located at memory
address: 00 000 000 00 001 000. Upon completion of the
subroutine, a RETURN instruction will return the computer to the
next step in the main program. |
3. CARRY BIT INSTRUCTIONS
There are two instructions which can be used to directly modify the
status of the Carry Bit. Each instruction requires one 8-bit byte.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CMC |
COMPLEMENT CARRY |
00 111 111 |
(Byte 1) |
| Operation: The Carry Bit is complemented. If it is initially
0, it is set to 1. If it is initially 1, it is reset to 0. |
| Status Bit Affected: Carry. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
STC |
SET CARRY |
00 110 111 |
(Byte 1) |
| Qperation: The Carry Bit is set to 1. |
| Status Bit Affected: Carry. |
4. NO OPERATION INSTRUCTION
There is one NO OPERATION instruction. It occupies a single 8-bit
byte.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
NOP |
NO OPERATION |
00 000 000 |
(Byte 1) |
| Operation: No operation occurs, and the Program Counter
proceeds to the next sequential instruction. Program excution
then continues. |
| Status Bits: Unaffected. |
B. SINGLE REGISTER INSTRUCTIONS
The ALTAIR 8800 has four single register instructions. Each
instruction occupies a single byte. Two of the instructions, INR
and DCR, have eight variances each. The variances are specified
according to any desired register, and the following register bit
patterns apply:
| Register |
Bit Pattern |
|---|
| B |
000 |
| C |
001 |
| D |
010 |
| E |
011 |
| H |
100 |
| L |
101 |
| Memory Reference M |
110 |
| A |
111 |
If Memory Reference M (110) is specified in the instruction byte,
the memory byte addressed by the contents of the H and L
registers is processed. The H register contains the most
significant 8 bits of the memory address and the L register
contains the least significant 8 bits of the address.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
INR |
INCREMENT REGISTER OR MEMORY |
00 (reg)
100 |
(Byte 1) |
| Operation: The specified byte is incremented by one. |
| Status Bits Affected: Zero, Sign, Parity, and Auxiliary Carry. |
Example: Assume the following instruction is present: 00 000
100. According to the table of register bit patterns given above, the
byte in register B is to be incremented by 1. If the initial byte
is 00 000 000, the incremented byte will be 00 000 001. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
DCR |
DECREMENT REGISTER OR MEMORY |
00 (reg)
101 |
(Byte 1) |
| Operation: The specified byte is decremented by one. |
| Status Bits Affected: Zero, Sign, Parity, and Auxiliary Carry. |
Example: Assume the following instruction is present: 00 001
101. According to the table of register bit patterns given above, the
byte in register C is to be decremented by 1. If the initial byte
is 00 000 001, the decremented byte will be 00 000 000. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CMA |
COMPLEMENT ACCUMULATOR |
00 101 111 |
(Byte 1) |
| Operation: Each bit in the accumulator is complemented (1s
become 0s and 0s become 1s). |
| Status Bits: Unaffected. |
Example: Assume the accumulator byte is 11 001 100. The
instruction CMA will complement each bit in the accumulator byte
as shown below:
| 11 001 100 |
Accumulator |
| —————— |
|
| 00 110 011 |
Complemented
Accumulator |
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
DAA |
DECIMAL ADJUST ACCUMULATOR |
00 100 111 |
(Byte 1) |
Operation: The 8-bit accumulator byte is converted into two
4-bit BCD (binary-coded-decimal) numbers. The instruction affected by
the Auxiliary Carry Bit.
The DAA instruction performs two operations:
- If the least significant 4 bits in the accumulator byte (bits
0-3) represent a BCD digit greater than 9 or if the Auxiliary
Carry Bit is set to 1, the four bits are automatically
incremented by 6. If not, the accumulator is unaffected.
- If the most significant 4 bits in the accumulator byte (bits 4-7)
represent a BCD digit greater than 9 or if the Carry Bit is set to
1 after the previous operation, the four bits are automatically
incremented by 6. If not, the accumulator is unaffected.
|
| Status Bits Affected: Zero, Sign, Parity, Carry, and Auxiliary
Carry. |
Example: Assume the accumulator byte is 10 100 100. The DAA
instruction will automatically consider the byte as two 4-bit bytes:
1010 0100. Since the value of the least significant 4 bits is less
than 9, the accumulator is initially unaffected. The value of the
most significant 4 bits is greater than 9, however, so the 4 bits are
incremented by 6 to give 1 0000. The most significant bit sets the
Carry Bit to 1, and the accumulator now contains: 00 000 100. |
C. REGLSTER PAIR INSTRUCTIONS
The ALTAIR 8800 has eight register pair instructions.
Each instruction occupies a single byte. Five of the instructions,
PUSH, POP, DAD, INX, and DCX, have four variances
each. The variances are specified according to any desired register
pair, and the following register pair bit patterns apply:
| Register Pair |
Bit Pattern |
|---|
| B and C |
00 |
| D and E |
01 |
| H and L |
10 |
| Flags and A |
11 |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
| PUSH |
PUSH DATA ONTO STACK |
11 (rp)0
101 |
(Byte 1) |
Operation: The contents of the specified register pair
(rp) are stored in two bytes of memory at an address
indicated by the Stack Pointer. The contents of the first
register are PUSHed into the address one less than the
address in the Stack Pointer. The contents of the second register
are PUSHed into the address two less than the address in
the Stack Pointer.
If the Status Bit Register and Accumulator (register pair PSW)
pair is specified, the first byte PUSHed into memory is the
Status Bit Register. This byte has the following format:
| Bit Position |
Contents |
|---|
| 7 |
Sign Bit |
| 6 |
Zero Bit |
| 5 |
0 |
| 4 |
Auxiliary Carry Bit |
| 3 |
0 |
| 2 |
Parity Bit |
| 1 |
1 |
| 0 |
Carry Bit |
For example, if the Carry Bit is set to 1 and all remaining status
bits are reset to 0, the Status Bit Register will contain the
following byte: 00 000 011.
After the PUSH instruction is implemented, the Stack Pointer is
automatically decremented by two.
|
| Status Bits: Unaffected. |
Example: Assume PUSH BC is implemented. The instruction byte
will have the following format: 11 000 101. The contents of
register pair BC will be stored in memory thusly: B will be
stored at the address in the Stack Pointer less one; C will be
stored at the address in the Stack Pointer less two. The Stack
Pointer will then be decremented by two. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
POP |
POP DATA OFF STACK |
11 (rp)0
001 |
(Byte 1) |
Operation: The contents of the specified register pair (rp)
are retrieved from the two bytes of memory at an address indicated
by the Stack Pointer. The contents of the memory byte at the Stack
Pointer address are loaded into the second register of the pair, and
the contents of the byte at the Stack Pointer address plus one are
loaded into the first register of the pair.
If the Status Bit Register and Accumulator (register pair PSW) pair
is specified, the contents of the byte at the Stack Pointer address
plus one are used to set or reset the status bits according to the
format provided in the description of the PUSH instruction.
After the POP instruction is implemented, the Stack Pointer is
automatically incremented by two.
|
| Status Bits Affected: None unless register pair PSW is specified. |
Example: The inverse of the example provided under the PUSH
instruction will illustrate operation of the POP instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
DAD |
DOUBLE ADD |
00 (rp)1
001 |
(Byte 1) |
Operation: The 16-bit number formed by the two bytes in the
specified register pair (rp) is added to the 16-bit number
formed by the two bytes in the H and L registers. The
result is stored in the H and L register pair. |
| Status Bits Affected: Carry. |
Example: Assume the 16-bit number formed by the two bytes in
register pair BC is 00 101 111 01 111 111. Assume the contents of
the H and L register pair form the 16-bit number 01 100 000
00 100 101. The instruction DAD BC (00 001 001) will add
the two numbers and store the result in the H and L register
pair. The result of the addition is: 10 001 111 10 100 100. Since no
carry occurred, the Carry Bit is reset to 0. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
INX |
INCREMENT REGISTER PAIR |
00 (rp)0
011 |
(Byte 1) |
Operation: The 16-bit number formed by the two bytes in the
specified register pair (rp) is incremented by one. |
| Status Bits: Unaffected. |
Example: Assume the INX instruction 00 100 011 is
present. According to the table of register pair bit patterns, the
16-bit number formed by the two bytes in the H and L
register pair will be incremented by one. If the initial 16-bit
number is 10 001 111 10 100 100, the new 16-bit number will be 10 001
111 10 100 101. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
DCX |
DECREMENT REGISTER PAIR |
00 (rp)1
011 |
(Byte 1) |
| Operation: The 16-bit number formed by the two bytes in the
specified register pair is decremented by one. |
| Status Bits: Unaffected. |
Example: Assume the DCX instruction 00 101 011 is
present. According to the table of register pair bit patterns, the
16-bit number formed by the two bytes in the H and L register
pair will be decremented by one. If the initial 16-bit number is 10
001 111 10 100 101, the new 16-bit number will be 10 001 111 10 100
100. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
XCHG |
EXCHANGE REGISTERS |
11 101 011 |
(Byte 1) |
Operation: The 16-bit number formed by the contents of the H
and L registers is exchanged with the 16-bit number formed by the
contents of the D and E registers. |
| Status Bits: Unaffected. |
Example: Assume the H register byte is 10 001 111 and the
L register byte is 10 000 011. Assume the D and E
register bytes are both 00 000 000. Implementation of the XCHG
instruction will exchange the contents of the two register pairs so
that the H and L register bytes are both 00 000 000 and the
D and E register bytes are, respectively, 10 001 111 and 10
10 000 011. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
XTHL |
EXCHANGE STACK |
11 100 011 |
(Byte 1) |
Operation: The byte stored in the L register is exchanged
with the memory byte addressed by the Stack Pointer. The byte stored
in the H register is exchanged with the memory byte at the
address one greater than that addressed by the Stack Pointer. |
| Status Bits: Unaffected. |
Example: The example provided under the XCHG instruction is
similar to the operation which occurs when the XTHL instruction
is implemented. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
SPHL |
LOAD SP FROM H AND
L |
11 111 001 |
(Byte 1) |
Operation: The 16-bit contents of the H and L registers
replace the contents of the Stack Pointer without affecting the
contents of the H and L registers. |
Example: Assume the H register byte is 10 001 111 and the
L register byte is 10 000 011. Assume the Stack Pointer
address is 00 001 100 01 111 111. Implementation of the SPHL
instruction will load the Stack Pointer with: 10 001 111 10 000 011.
The contents of the H and L registers will remain unchanged. |
D. ROTATE ACCUMULATOR INSTRUCTIONS
This is a special set of four instructions which apply only to the
ALTAIR 8800’s accumulator. Only one byte of instruction is required,
and no memory or register variances apply.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RLC |
ROTATE ACCUMULATOR LEFT |
00 000 111 |
(Byte 1) |
| Operation: The accumulator byte is rotated one bit position
to the left. The 7 bit position now occupies the 0 bit position
and the Carry Bit is set with the value of the 7 bit before
rotation. |
| Status Bits Affected: Carry. |
Example: Assume the accumulator byte is 10 001 000 and the
RLC instruction is present. The Carry Bit is set to equal the
value of the accumulator byte’s 7 bit (1), and the contents of
the accumulator are rotated one bit position to the left. The 7
bit now occupies the 0 bit: 00 010 001. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RRC |
ROTATE ACCUMULATOR RIGHT |
00 001 111 |
(Byte 1) |
| Operation: The accumulator byte is rotated one bit position
to the right. The 0 bit position now occupies the 7 bit position
and the Carry Bit is set with the value of the 0 bit before
rotation. |
| Status Bits Affected: Carry. |
| Example: Assume the accumulator byte is 10 001 000 and the
RRC instruction is present. The Carry Bit is set equal to the
value of the accumulator byte’s 0 bit (0), and the contents of
the accumulator are rotated one bit position to the right. The 0
bit now occupies the 7 bit: 01 000 100. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RAL |
ROTATE ACCUMULATOR LEFT
THROUGH CARRY |
00 010 111 |
(Byte 1) |
| Operation: The accumulator byte is rotated one bit position
to the left through the Carry Bit. The 7 bit position then
occupies the Carry Bit and the Carry Bit occupies the 0 bit
position. |
| Status Bits Affected: Carry. |
Example: Assume the accumulator byte is 10 001 000, the Carry
Bit is 1, and the RAL instruction is present. The contents of the
accumulator are rotated one bit left through the Carry Bit. The 7
bit now occupies the Carry Bit (1) and the Carry Bit now occupies
the 0 bit: 00 010 001. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RAR |
ROTATE ACCUMULATOR RIGHT
THROUGH CARRY |
00 011 111 |
(Byte 1) |
| Operation: The accumulator byte is rotated one bit position
to the right through the Carry Bit. The 0 bit position now
occupies the Carry Bit and the Carry Bit occupies the 7 bit
position. |
| Status Bits Affected: Carry. |
Example: Assume the accumulator byte is 10 001 000, the Carry
Bit is 1, and the RAR instruction is present. The contents of the
accumulator are rotated one bit position right through the Carry
Bit. The 0 bit now occupies the Carry Bit, and the Carry Bit now
occupies the 7 bit: 11 000 100. |
E. DATA TRANSFER INSTRUCTIONS
Data can be conveniently transferred between registers or between the
memory and registers of the ALTAIR 8800. Certain of these operations
are direct data transfers and no other operation is involved. For
example, the MOV instruction causes a byte of data to be
transferred from one register (the source register) to another
register (the destination register). Other data transfers are
accompanied by an arithmetic or logical operation. For example, the
ADD instruction adds the contents of a specified register to the
contents of the accumulator.
Still another class of data transfer instructions concerns only the
accumulator and the H and L register pair. For example, the
STA instruction causes the contents of the accumulator to replace
the byte of data stored at a specified memory address.
This section describes fifteen separate data transfer instructions,
but it is important to note that many other instructions also involve
the transfer of data (e.g. PUSH, POP, DAD, XCHG,
XTHL, SPHL, etc.). However, it is more appropriate to the
efficient organization of this operating manual to describe these
instructions elsewhere.
The data transfer instructions described in this section are grouped
into three subdivisions. The first subdivision is Data Transfers
(MOV, STAX, and LDAX). The second is Register/Memory to
Accumulator Transfers (ADD, ADC, SUB, SBB, ANA,
XRA, ORA, and CMP). And the third is Direct Addressing
Transfers (STA, LDA, SHLD, and LHLD).
1. DATA TRANSFER INSTRUCTIONS
There are three data transfer instructions and each is unconditional.
Each of the three instructions has at least two variances, The
variances are determined by register or memory addresses which are
specified by the programmer.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
MOV |
MOVE DATA |
01 (DDD)
(SSS) |
(Byte 1) |
Operation: The contents of (SSS) (the source register) are
moved to (DDD) (the destination register). The contents of
(SSS) remain unchanged. The following bit patterns for the source
and destination registers apply:
| Register |
Bit Pattern |
|---|
| B |
000 |
| C |
001 |
| D |
010 |
| E |
011 |
| H |
100 |
| L |
101 |
| Memory Reference M |
110 |
| A |
111 |
The source and destination registers cannot both equal 110.
|
| Status Bits: Unaffected. |
Example: Assume it is necessary to transfer the contents of
register E to the accumulator. By referring to the register
bit pattern table provided above, an appropriate MOV
instruction can be formulated: 01 111 011. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
STAX |
STORE ACCUMULATOR |
00
0(X)0
010 |
(Byte 1) |
Operation: The contents of the accumulator are stored in a
memory address specified by registers B and C or registers
D and E. Registers B and C are specified by a 0 at
the 4 bit position (X). Registers D and E are specified
by a 1 at the 4 bit position (X). |
| Status Bits: Unaffected. |
Example: Assume it is necessary to store the contents of the
accumulator at a memory address specified by registers D
and E. The appropriate STAX instruction is: 00 010
010. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
LDAX |
LOAD ACCUMULATOR |
00
0(X)1
010 |
(Byte 1) |
Operation: The contents of the memory address specified by
registers B and C or by registers D and E replace
the contents of the accumulator, Registers B and C are
specified by a 0 at the 4 bit position (X). Registers
D and E are specified by a 1 at the 4 bit position (X). |
| Status Bits: Unaffected. |
Example: Assume it is necessary to load the accumulator with
the contents of a memory address specified by registers B and
C, The appropriate LDAX instruction is: 00 001 010. |
2. REGISTER/MEMORY TO ACCUMULATOR TRANSFERS
There are eight Register/Memory to Accumulator Transfers and each is
unconditional. Each of the eight instructions has eight variances
determined by registers specified by the programmer, The following bit
patterns for each of the registers apply:
| Register |
Bit Pattern |
|---|
| B |
000 |
| C |
001 |
| D |
010 |
| E |
011 |
| H |
100 |
| L |
101 |
| Memory Address M |
110 |
| A |
111 |
Four of the instructions involve arithmetic (add or subtract)
operations, The remaining four involve logical operations.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
ADD |
ADD REGISTER/ACCUMULATOR TO
MEMORY |
10 000
(reg) |
(Byte 1) |
Operation: The contents of the specified register (reg) are
added to the contents of the accumulator. |
| Status Bits Affected: Carry, Sign, Zero, Parity, and Auxiliary
Carry. |
Example: Assume it is necessary to add the contents of register
B to the accumulator. Referring to the register bit pattern
table given above, the appropriate instruction is: 10 000 000. If
the data bytes at register B and the accumulator are 11 010 100
and 01 100 010 respectively, the following addition will be
performed:
| 11 010 100 |
Register B
Byte |
| 01 100 010 |
Accumulator
Byte |
| —————— |
|
| 100 110 110 |
New
Accumulator
Byte |
Since the new accumulator byte has nine bits, the Carry Bit will be
set to 1 to indicate a carry has occurred.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
ADC |
ADD REGISTER/MEMORY AND
CARRY TO ACCUMULATOR |
10 001
(reg) |
(Byte 1) |
Operation: The contents of the specified register (reg)
and the content of the Carry Bit are added to the accumulator. |
| Status Bits Affected: Carry, Sign, Zero, Parity, and Auxiliary
Carry. |
Example: Assume it is necessary to add the contents of register
C and the content of the Carry Bit to the accumulator. Referring
to the register bit pattern table given above, the appropriate
instruction is: 10 001 001. If the data bytes at register C
and the accumulator are 00 100 011 and 01 011 100 and the Carry
Bit is 1, the following addition will be performed:
| 00 100 011 |
Register C
Byte |
| 01 011 100 |
Accumulator
Byte |
| 1 |
Carry Bit |
| —————— |
|
| 100 000 000 |
New
Accumulator
Byte |
If the new accumulator byte had nine bits, the extra bit would
set the Carry Bit to 1.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
SUB |
SUBTRACT REGISTER/MEMORY
FROM ACCUMULATOR |
10 010
(reg) |
(Byte 1) |
Operation: The contents of the specified register are subtracted
from the contents of the accumulator. The ALTAIR 8800 achieves
subtraction by. means of a simple addition process called two’s
complement arithmetic. If there are only eight bits in the result, no
carry bit is present. This means a borrow occurred, and the Carry
Bit is set to 1. Note that this operation is the inverse of what
occurs in an ADD instruction. |
| Status Bits Affected: Carry Sign, Zero, Parity, and Auxiliary
Carry. |
Example: Assume it is necessary to clear the accumulator of
its contents. An efficient way to achieve this requirement is to
implement a SUB A instruction (10 010 111) where A
specifies the accumulator variance of the SUB instruction.
Implementation of this instruction will cause the contents of the
accumulator to be subtracted from itself. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
SBB |
SUBTRACT REGISTER/MEMORY
FROM ACCUMULATOR WITH BORROW |
10 011
(reg) |
(Byte 1) |
| Operation: The content of the Carry Bit is added to the contents
of the specified register and the result is then subtracted from
the accumulator using two’s complement arithmetic. |
| Status Bits Affected: Carry, Sign, Zero, Parity, and Auxiliary
Carry. |
Example: Assume that the SBB instruction is implemented for
the B variance (10 011 000). The contents of register B
will be added to the carry bit, and the result will then be
subtracted from the accumulator. Status bits will be set or reset as
appropriate. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
ANA |
LOGICAL AND REGISTER/MEMORY
WITH ACCUMULATOR |
10 100
(reg) |
(Bytte 1) |
Operation: The content of the specified register is logically
ANDed with the contents of the accumulator. The Carry Bit is
reset to 0. |
| Status Bits Affected: Carry, Zero, Sign, and Parity. |
Example: Assume the content of register L is 10 001 100 and
the content of the accumulator is 10 000 101. The L variant of
ANA instruction (10 100 101) will then cause the contents of
the two registers to be ANDed with one another bit-by-bit.
Since the logical ANDing of two bits is 1 only if both bits are
1, the following procedure occurs:
| 10 001 100 |
Register L |
| 10 000 101 |
Accumulator |
| —————— |
|
| 10 000 100 |
Register L
AND
Accumulator |
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
XRA |
LOGICAL EXCLUSIVE-OR
REGISTER/MEMORY WITH
ACCUMULATOR |
10 101
(reg) |
(Byte 1) |
Operation: The content of the specified register is logically
EXCLUSIVE-ORed with the contents of the accumulator. The
Carry Bit is reset to 0. |
| Status Bits Affected: Carry, Sign, Zero, and Parity. |
Example: Since the EXCLUSIVE-ORing of two bits is 1 only if
the values of the bits are different, the XRA instruction can be
used to clear the accumulator to 0. This function is implemented by
means of the instruction XRA and the variance A. The
resulting statement is 10 101 111 (see the table of register bit
patterns given above).
The XRA instruction can also be used to monitor the status of
individual bits in a byte which has been designated a condition byte.
For example, assume a byte has been designated to record eight
separate true-false conditions wherein a 1 is true and a 0 is false.
In order to check whether or not any of the conditions have changed,
the original data byte can be moved to the accumulator and
EXCLUSIVE-ORed with the updated data byte. Conditions which
have not changed will produce a 0 bit and conditions which have
changed will produce a 1 bit.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
ORA |
LOGICAL OR REGISTER/MEMORY
WITH ACCUMULATOR |
10 110
(reg) |
(Byte 1) |
Operation: The content of the specified register is logically
ORed with the content of the accumulator. The Carry Bit is
reset to zero. |
| Status Bits Affected: Carry, Zero, Sign, and Parity. |
Example: Since the ORing of two bits is 0 only if the
value of each bit is 0, the ORA instruction can be used to
set a group of bits to a series of 1s. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CMP |
COMPARE REGISTER/MEMORY WITH
ACCUMULATOR |
10 111
(reg) |
(Byte 1) |
| Operation: The content of the specified register is compared
with the content of the accumulator by subtracting the former
from the latter. The contents of the register and accumulator
are unaffected by this operation, and the status bits are set or
reset as appropriate. |
| Status Bits Affected: Carry, Sign, Zero, and Parity (Note:
The sense of the Carry Bit is reversed if one byte is plus and
the other is minus). |
Example: The CMP instruction is useful in determining
when the content of any particular register equals that of the
accumulator. If the two bytes are equal, the subtraction will
give a 0 result, and the Zero Status Bit will be set to 1. If
the register contents are greater than the accumulator contents,
the Carry Bit will be set to 1 since a subtraction has occurred.
If the register contents are less than the accumulator contents,
the Carry Bit will be reset to 0. |
3. DIRECT ADDRESSING INSTRUCTIONS
The four instructions described in this section are used to store the
contents of the accumulator and the H and L registers in the memory or
to load the accumulator and H and L ce registers with data from the
memory. All four instructions require three bytes. The first byte is
the specific instruction, and the second and third bytes provide the
memory address.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
STA |
STORE ACCUMULATOR DIRECT |
00 110 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: The contents of the accumulator are stored in the
memory at the address specified in bytes 2 and 3. |
| Status Bits: Unaffected. |
Example: Assume the accumulator byte is 00 010 110 and a STA
instruction is present with the following memory address:
| 01 000 000 |
(Byte 2) |
| 01 000 001 |
(Byte 3) |
The accumulator byte will then be stored at this memory address.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
LDA |
LOAD ACCUMULATOR DIRECT |
00 111 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: The accumulator is loaded with the contents of the
byte at the memory address given by bytes 2 and 3 of the instruction. |
| Status Bits: Unaffected. |
Example: The inverse of the example given in the STA
instruction will illustrate operation of the LDA instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
SHLD |
STORE H AND L DIRECT |
00 100 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
Operation: The contents of the L register are stored in the
memory at the address specified in bytes 2 and 3. The contents of the
H register are stored in the memory at the next higher address. |
| Status Bits: Unaffected. |
Example: Assume the L register byte is 00 101 100, the H
register byte is 00 101 111, and an SHLD instruction is present
with the following address:
| 01 000 101 |
(Byte 2) |
| 01 110 101 |
(Byte 3) |
The L register byte will then be stored at this memory address,
and the H register byte will be stored at the next highest
address.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
LHLD |
LOAD H AND L DIRECT |
00 101 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
Operation: The L register is loaded with the contents of the
byte at the memory address given by bytes 2 and 3. The H
register is loaded with the contents of the byte at the next higher
memory address. |
| Status Bits: Unaffected. |
Example: The inverse of the example given in the SHLD
instruction will illustrate operation of the LHLD instruction. |
G. BRANCHING INSTRUCTIONS
The ALTAIR 8800 has an extensive branching capability. Branching
permits the computer to jump from one step in the program to another.
Branching also permits the computer to call a specified set of
instructions from memory and insert it into the program. A return
feature permits the computer to resume normal operation after the
specified instruction set is executed.
Branching is one of the most important capabilities of a computer.
Jumping from one point in the program to another, for example, saves
time, and calling a special set of instructions from memory means a
frequently used instruction sequence need be stored at only one place
in memory. The result is an important increase in computer processing
speed and efficiency. Branching also adds to the economy of a
computer since less memory is required to accomplish complex programs.
And the ability to call frequently used instruction sets from memory
can save considerable programming time.
The term subroutine is used to describe a special set of instructions
stored in memory. Typical subroutines might include instruction sets
for calculating trigonometric functions and square roots or making
complex logical comparisons. Each of these subroutines can be quite
lengthy. If a program requires a dozen or more trigonometric
operations and several square root extractions, it is obvious that the
use of subroutines can save considerable programming time and memory
space.
Branching instructions can be either conditional or unconditional. A
conditional branch means a particular branching operation is
accomplished only if a specified condition is met. For example, a
typical conditional branch instruction is CZ (CALL IF ZERO). If
the zero bit is indeed zero when the CZ instruction is processed,
the Program Counter will automatically move to the address in memory
specified in the two address bytes which follow the CZ instruction
in the program.
Unconditional branching causes a branch to occur without the necessity
for meeting certain specified conditions.
Branching instructions require either one or three bytes per
instruction. The first byte is the actual instruction while the
second and third bytes are, respectively, the low and high memory
addresses. The address bytes tell the Program Counter where to
move. The instructions which require only one byte need no memory
addresses since some of the bits in the byte refer the Program Counter
to certain registers or the Stack Pointer, either of which contains
the necessary addressing information.
1. JUMP INSTRUCTIONS
JUMP instructions permit the normal execution sequence of a program to
be either conditionally or unconditionally altered. For example, a
program might include a set of instructions to be executed if the
result of a previous operation is greater than zero. If, however, the
result is zero, the set of instructions becomes superfluous and
unnecessary. The program, therefore, includes a JUMP statement
which instructs the computer to advance to any specified address past
the instruction set. Since the jump would be implemented only if the
result of the preceeding operation were zero, this would be a
conditional branching operation. The actual machine language mnemonic
for this particular instruction is JZ (JUMP IF ZERO).
All but one of the ten JUMP instructions require three bytes. The
first byte is the specific machine language instruction, while the
second and third bytes are, respectively, the low and high memory
addresses for the portion of the program to ww be selected by the
Program Counter if a jump is implemented. The PCHL instruction
requires only the initial machine language instruction byte since the
memory locations to which the program jumps are known by the computer.
The memory locations in this case happen to be the H and L
Registers, the contents of which are placed into the Program Counter.
With the exception of the PCHL and JMP instructions, all
JUMP instructions are conditional. If a specified condition is
true, the Program Counter automatically advances to the address
specified in the instruction. If the specified condition is not true,
the program continues its sequential execution and a jump does not
occur.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
PCHL |
LOAD PROGRAM COUNTER |
11 101 001 |
(Byte 1) |
Operation: The Program Counter jumps to the Memory address
specified by the contents of the H and L Registers. The most
significant 8 bits of the Program Counter are loaded with the
contents of the H Register and the least significant 8 bits of
the Program Counter are loaded with the contents of the L
Register. |
| Status Bits: Unaffected. |
Example: Assume the contents of the H and L Registers are
as follows:
| H: |
10 111 000 |
| L: |
11 010 110 |
Instruction PCHL will automatically transfer this Memory
address to the Program Counter as shown below:
| |
Most Significant |
Least Significant |
|---|
| Program Counter: |
10 111 000 |
11 010 110 |
The program will now continue to execute after having jumped to the
new address specified in the Program Counter.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JMP |
JUMP |
11 000 011 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: The Program Counter jumps unconditionally to the
Memory address specified in bytes 2 and 3 and the program continues
to execute from the new location. |
| Status Bits: Unaffected. |
Example: Assume the JMP instruction and address bit pattern
is as follows:
| 11 000 011 |
(Byte 1) |
| 10 111 000 |
(Byte 2) |
| 11 010 110 |
(Byte 3) |
The Program Counter will jump to the address in Memory specified
by bytes 2 and 3 and program execution will continue from the new
address.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JC |
JUMP IF CARRY |
11 011 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status
of the Carry Bit is 1, a carry has occurred and the Program
Counter jumps to the address specified in bytes 2 and 3. Program
execution then continues from the new address. If the Carry Bit is 0,
no carry has occurred and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume the Carry Bit is 1 and a JC instruction is
present. The Program Counter will then jump to the address specified
in bytes 2 and 3 and the program will continue at the new address. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JNC |
JUMP IF NO CARRY |
11 010 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status
of the Carry Bit is 0, no carry has occurred, and the Program
Counter jumps to the address specified in bytes 2 and 3. Program
execution then continues from the new address. If the Carry Bit is
1, a carry has occurred and the program continues sequential
execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the JC
instruction will illustrate operation of the JNC instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JZ |
JUMP IF ZERO |
11 001 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Zero Bit is 1, a zero is present and the Program Counter jumps to
the address specified in bytes 2 and 3. Program execution then
continues from the new address. If the Zero Bit is 0, a zero is not
present and the program continues sequential operation. |
| Status Bits: Unaffected. |
Example: Assume the Zero Bit is 1 (zero present) and a JZ
instruction is present. The Program Counter will then jump to the
address specified in bytes 2 and 3 and the program will continue at
the new address. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JNZ |
JUMP IF NOT ZERO |
11 000 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
Operation: This is a conditional instruction. If the status of
the Zero Bit is 0 (zero not present) and a JNZ instruction is
present, the Program Counter jumps to the address specified in bytes
2 and 3. Program execution then continues from the new address. If
the Zero Bit is 1, a zero is present, and the program continues
sequential operation. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the JZ
instruction will illustrate operation of the JNZ instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JM |
JUMP IF MINUS |
11 111 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Sign Bit is 1 (a negative result), the Program Counter jumps to
the address specified in bytes 2 and 3. Program execution then
continues from the new address. If the Sign Bit is 0, the result is
positive and the program continues sequential operation. |
| Status Bits: Unaffected. |
Example: Assume the Sign Bit is 1 indicating a negative result
and the JM instruction is present. The Program Counter will then
jump to the address specified in bytes 2 and 3 of the instruction and
the program will continue at the new address. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JP |
JUMP IF PLUS |
11 110 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Sign Bit is 0 (a positive result), the Program Counter jumps to
the address specified in bytes 2 and 3. Program execution then
continues from the new address. If the Sign Bit is 1, the result is
negative and the program continues sequential operation. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the JM
instruction will illustrate operation of the JP instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JPE |
JUMP IF PARITY IS EVEN |
11 101 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Parity Bit is 1 (a result with even parity), the Program Counter
jumps to the address specified in bytes 2 and 3. Program execution
then continues from the new address. If the Parity Bit is 0, the
parity is odd and the program continues sequential operation. |
| Status Bits: Unaffected. |
Example: Assume the Parity Bit is 1 indicating the result has
even parity and the JPE instruction is present. The Program
Counter will jump to the address specified in bytes 2 and 3 and the
program will continue at the new address. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
JPO |
JUMP IF PARITY IS ODD |
11 100 010 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Parity Bit is 0 (a result with odd parity), the Program Counter
jumps to the address specified by bytes 2 and 3. Program execution
then continues from the new address. If the Parity Bit is 1, the
parity is even and the program continues sequential operation. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the JPE
instruction will illustrate operation of the JPO instruction. |
2. CALL INSTRUCTIONS
CALL instructions cause a program to execute a subroutine stored
at a specified location in memory. The CALL instruction may be either
conditional or unconditional. Many subroutines are called unconditionally.
For example, the calculation sequence for extracting a square root is
relatively lengthy. In a program which requires frequent square root
extractions, considerable programming time and memory space 1 can be
saved by writing a single square root extraction subroutine. This
subroutine can then be stored in memory and called by the program each
time it is needed.
Conditional CALL instructions are available also. They permit a great
deal of flexibility since the programmer can instruct the computer to
make logical decisions about the status of the program at any specified
point. A subroutine can then be called if a specified condition is met.
When a subroutine has been executed, the Program Counter returns to
the next step in the main program by means of a special RETURN
instruction. This instruction is described in the next section.
All the CALL instructions require three bytes. The first byte is the
specific machine language instruction while the second and third bytes
are, respectively, the low and high Memory addresses for the first
instruction of the subroutine.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CALL |
CALL |
11 001 101 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: The Program Counter unconditionally moves to the
Memory address specified in bytes 2 and 3. The subroutine at the
new location is then executed. |
| Status Bits: Unaffected. |
Example: Assume the CALL instruction and address bit pattern
is as follows:
| 11 001 101 |
(Byte 1) |
| 10 101 111 |
(Byte 2) |
| 11 111 010 |
(Byte 3) |
The Program Counter will move to the address in Memory specified by
bytes 2 and 3 and the subroutine at that location will then be
executed.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CC |
CALL IF CARRY |
11 011 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This a conditional instruction. If the status of the
Carry Bit is 1, a carry has occurred and the Program Counter moves to
the address specified in bytes 2 and 3. The subroutine at this
location is then executed. If the Carry Bit is 0, no carry has
occurred, and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume the Carry Bit is 1 and the CC instruction is
present. The Program Counter will then jump to the address specified
in bytes 2 and 3 and the subroutine at that location will be
executed. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CNC |
CALL IF NO CARRY |
11 010 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Carry Bit is 0, a carry has not occurred, and the Program Counter
moves to the address specified in bytes 2 and 3. The subroutine at
that location is then executed. If the Carry Bit is 1, a carry has
occurred, and the Program Counter continues sequential execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the CC
instruction will illustrate operation of the CNC instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CZ |
CALL IF ZERO |
11 001 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Zero Status Bit is 1, a zero is present, and the Program Counter
moves to the address specified in bytes 2 and 3. The subroutine at
this location is then executed. If the Zero Status Bit is 0, no zero
is present, and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume the Zero Status Bit is 1 and the CZ
instruction is present. The Program Counter will then move to the
address specified in bytes 2 and 3, and the subroutine at that
location will be executed. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CNZ |
CALL IF NOT ZERO |
11 000 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Zero Status Bit is 0, a zero is not present, and the Program
Counter moves to the address specified in bytes 2 and 3. The
subroutine at this location is then executed. If the Zero Status Bit
is 1, a zero is present, and the program continues sequential
execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the CZ
instruction will illustrate operation of the CNZ instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CM |
CALL IF MINUS |
11 111 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Sign Bit is 1 (a negative result), the Program Counter moves to
the address specified in bytes 2 and 3. The subroutine at this
location is then executed. If the Sign Bit is 0, the result is
positive, and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume the Sign Bit is 1 and the CM instruction is
present. The Program Counter will then move to the address specified
in bytes 2 and 3, and the subroutine at that location will be
executed. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CP |
CALL IF PLUS |
11 110 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Sign Bit is 0 (a positive result), the Program Counter moves to
the address specified in bytes 2 and 3. The subroutine at this
location is then executed. If the Sign Bit is 1, the result is
negative, and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the CM
instruction will illustrate operation of the CP instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CPE |
CALL IF PARITY IS EVEN |
11 101 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Parity Bit is 1 (a result with even parity), the Program Counter
moves to the address specified in bytes 2 and 3. The subroutine at
this location is then executed. If the Parity Bit is 0, the parity
is odd, and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume the status of the Parity Bit is 1 and a CPE
instruction is present. The Program Counter will then move to the
address specified in bytes 2 and 3, and the subroutine at that
location will be executed. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
CPO |
CALL IF PARITY IS ODD |
11 100 100 |
(Byte 1) |
| |
(Low
Address) |
(Byte 2) |
| |
(High
Address) |
(Byte 3) |
| Operation: This is a conditional instruction. If the status of
the Parity Bit is 0 (a result with odd parity), the Program Counter
moves to the address specified in bytes 2 and 3. The subroutine at
this location is then executed. If the Parity Bit is 1, the parity is
even, and the program continues sequential execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the CPE
instruction will illustrate operation of the CPO instruction. |
3. RETURN INSTRUCTIONS
When a CALL subroutine instruction is executed, the address of the
next sequential instruction in the program is automatically pushed
onto the stack. The subroutine may have one or more RETURN statements.
An unconditional RETURN instruction is included at the end of most
subroutines. This instruction pops the last address stored in the
stack by the CALL instruction from the stack and onto the Program
Counter. When the subroutine has been executed, the program resumes
sequential execution at the address following the initial CALL
subroutine instruction.
Conditional RETURN instructions may be scattered throughout a
subroutine. If the required condition is met, the program resumes
sequential execution in the manner just described.
Since the program address to which the Program Counter re- ww turns
upon receiving a RETURN instruction is already stored on the stack,
RETURN instructions require only one byte. The last bit in the byte
is 1 for an unconditional RETURN and 0 for conditional RETURNs.
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RET |
RETURN |
11 001 001 |
(Byte 1) |
Operation: The subroutine is completed, and the Program Counter
automatically and unconditionally returns to the next address
following the initial CALL subroutine instruction. |
| Status Bits: Unaffected. |
Example: Assume two of the instruction statements in an
ALTAIR 8800 program are as follows:
| CALL |
11 001 101 |
(Byte 1) |
| (Low Address) |
(Byte 2) |
| (High Address) |
(Byte 3) |
| CMA |
00 101 111 |
(Byte 1) |
Upon receiving the CALL instruction, the Program Counter moves to
the address in Memory specified by bytes 2 and 3. Simultaneously, the
address of the next sequential instruction (CMA) is pushed onto
the stack.
The final instruction in the subroutine must be an unconditional
RETURN (only if you wish to return). When execution of the
subroutine is complete and the RET instruction is reached, the
Program Counter automatically receives the address of the next
instruction in the main program from the stack (CMA), and
sequential execution resumes.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RC |
RETURN IF CARRY |
11 011 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the| Carry
Bit is 1, a carry has occurred and the Program Counter automatically
returns to the next, sequential address in the main program following
the initial CALL subroutine instruction. |
| Status Bits: Unaffected. |
Example: Assume three of the instructions in a subroutine are as
as follows:
| RAL |
00 010 111 |
(Byte 1) |
| RC |
11 011 000 |
(Byte 1) |
| STAX |
00 000 010 |
(Byte 1) |
If the status of the Carry Bit is 1 when the RC instruction is
reached, a carry has occurred and the Program Counter automatically
returns to the next sequential address in the main program
following the initial CALL subroutine instruction. If the
status of the Carry Bit is 0, the subroutine continues sequential
execution by implementing the STAX instruction.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RNC |
RETURN IF NO CARRY |
11 010 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Carry
Bit is 0, a carry has not occurred and the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL subroutine instruction. If the
status of the Carry Bit is 1, a carry has occurred, and the
subroutine continues sequential execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the RC
instruction will illustrate operation of the RNC instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RZ |
RETURN IF ZERO |
11 001 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Zero
Status Bit is 1, a 0 is present and the Program Counter automatically
returns to the next sequential address in the main program following
the initial CALL subroutine instruction. If the status of the
Zero Status Bit is 0, a zero is not present and the subroutine
continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume three of the instructions in a subroutine are as
follows:
| ADD |
10 000 101 |
(Byte 1) |
| RZ |
11 001 000 |
(Byte 1) |
| LDAX |
00 011 010 |
(Byte 1) |
If the status of the Zero Status Bit is 1 when the RZ instruction
is reached, a zero result is present and the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL instruction. If the status
of the Zero Status Bit is 0, the subroutine continues execution by
implementing the LDAX instruction.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RNZ |
RETURN IF NOT ZERO |
11 000 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Zero
Status Bit is 0, a zero result is not present and the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL subroutine instruction. If the
status of the Zero Status Bit is 1, a zero result is present, and the
subroutine continues sequential execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the RZ
instruction will illustrate operation of the RNZ instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RM |
RETURN IF MINUS |
11 111 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Sign
Bit is 1 (a negative result), the Program Counter automatically
returns to the next sequential address in the main program
following the initial CALL subroutine instruction. If the status
of the Sign Bit is 0 (a positive result), the subroutine continues
sequential execution. |
| Status Bits: Unaffected. |
Example: Assume three of the instructions in a subroutine are as
follows:
| SUB |
10 010 001 |
(Byte 1) |
| RM |
11 111 000 |
(Byte 1) |
| LDAX |
00 011 010 |
(Byte 1) |
If the status of the Sign Bit is 1 when the RM instruction is
reached, a negative result is present, and the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL subroutine instruction. If the
status of the Sign Bit is 0, the subroutine continues sequential
execution by implementing the LDAX instruction.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RP |
RETURN IF PLUS |
11 110 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Sign
Bit is 0 (a positive result), the Program Counter automatically
returns to the next sequential address in the program following the
initial CALL subroutine instruction. If the status of the Sign
Bit is 1 (a negative result), the subroutine continues sequential
execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the RM
instruction will illustrate operation of the RP instruction. |
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RPE |
RETURN IF PARITY IS EVEN |
11 101 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Parity
Bit is 1 (a result with even parity), the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL subroutine instruction. If the
status of the Parity Bit is 0 (a result with odd parity), the
subroutine continues sequential execution. |
| Status Bits: Unaffected. |
Example: Assume three of the instructions in a subroutine are
as follows:
| CMP |
10 111 001 |
(Byte 1) |
| RPE |
11 101 000 |
(Byte 1) |
| RLC |
00 000 111 |
(Byte 1) |
If the status of the Parity Bit is 1 when the RPE instruction is
reached, the parity of the result is even, and the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL subroutine instruction. If the
status of the Parity Bit is odd, the subroutine continues sequential
execution by implementing the RLC instruction.
|
| MNEMONIC |
INSTRUCTION |
BINARY CODE |
POSITION |
|---|
RPO |
RETURN IF PARITY IS ODD |
11 100 000 |
(Byte 1) |
Operation: This is a conditional instruction which may be
inserted before the end of a subroutine. If the status of the Parity
Bit is 0 (a result with odd parity), the Program Counter
automatically returns to the next sequential address in the main
program following the initial CALL subroutine instruction. If the
status of the Parity Bit is 1 ( a result with odd parity), the
subroutine continues sequential execution. |
| Status Bits: Unaffected. |
Example: The inverse of the example provided under the RPE
instruction will illustrate operation of the RPO instruction. |